VeriSilicon's Vivante DeWarp Processor provides high-performance DeWarp processing for the correction of the distortion that is introduced in images produced by fisheye and wide-angle lenses. It is implemented with a line/tile-cache based architecture. With configurable address mapping look up tables and per tile processing, it can successfully generate corrected output images.

This DeWarp IP is designed for easy integration into SoCs, providing high performance, high quality, low power consumption, and the smaller silicon footprint for its class. Its core is delivered as synthesizable RTL. DeWarp IP is technology independent, which can be synthesized using a variety of libraries. Dynamic power consumption is minimized by extensive use of multi-level hierarchical clock gating.