• Independently work on the design of ASIC function blocks in terms of Design Spec, Architecture definition, block design, RTL coding, logic synthesis and timing analysis (STA);

• Cooperation with verification engineer, finish verification job and responsible for design quality. Review verification plan, Simulation & Debug, cdc check;

• As SoC owner, work closely with system engineers, physical implementation designers, and testing engineers to do functional verification, floorplan, timing optimization/closure and DFT& ATE testing consideration.

• Master/PhD degree in EE/CS related specialties;

• Mastery of EDA tools(Synopsys or Cadence, VCS, Xcelium, DC, PT etc.) and capability of solving technical issues as below is a must: Design specification, RTL coding and style critique, block design, chip-level integration; logic synthesize and timing analyze (STA);System C modeling, System Verilog based on UVM methodology;

• Relevant digital design experiences (on FPGA or ASIC, including course projects);

• Familiar with C/C++, perl, python etc;

• Knowledge of computer architecture (ARM or RISC-V) & on chip bus AMBA/NOC is a plus;

• Knowledge of Audio Video interfaces: MIPI/HDMI/DP/SPDIF/I2S etc. is a plus;

• Knowledge of interfaces USB/PCIe/Ethernet/DDR/SD/eMMC/SPI/CAN etc. is a plus;

• Knowledge of AI or Video Codec is a plus;

• Self-motivated, team work, and good communication skills in Chinese and English.

• Independently work on the verification of ASIC function blocks in terms of Verification Plan, Build Test bench, Develop Test cases, Simulation & Debug;

• Setup IP/chip level verification env, modeling;

• RTL/Gate-level simulation/regression. Code/function coverage analysis and closure.

• Master/PhD degree in EE/CS related specialties;

• Familiar with design and verification languages (Verilog, SystemVerilog, SVA etc.);

• Relevant digital design experiences (on FPGA or ASIC, including course projects);

• Familiar with C/C++, perl, python etc;

• Knowledge of computer architecture (ARM or RISC-V) & on chip bus AMBA/NOC is a plus;

• Knowledge of Audio Video interfaces: MIPI/HDMI/DP/SPDIF/I2S etc. is a plus;

• Knowledge of interfaces USB/PCIe/Ethernet/DDR/SD/eMMC/SPI/CAN etc. is a plus;

• Knowledge of AI or Video Codec is a plus;

• Self-motivated, team work, and good communication skills in Chinese and English.

• Capable of contributing to and working on the chip and sub-blocks in terms of synthesize, timing optimization and sign-off;

• Capable of contributing to and working on the chip and sub-blocks in terms of Design PPA;

• Capable of contributing to and working on the chip and sub-blocks in terms of SDC writing change and hand-off;

• Capable of contributing to and working on the chip and sub-blocks in terms of DFT coverage analysis;

• Design test logic, insert Scan chain, MBIST, Boundary Scan circuits, finish DFT patterns generation and simulation;

• Work closely with physical implementation engineers, to solve floorplan, timing analysis, optimization/closure.

• Master/PhD degree in EE/CS related specialties;

• Course knowledge and project experience in the related areas;

• Programming skills in Verilog HDL and System Verilog;

• Familiar with EDA tool, Such as Synopsys VCS、Verdi, Cadence IUS, Mentor QuestaSim;

• Knowledge of SoC design techniques is a plus;

• Knowledge of physical implementation techniques is a plus;

• Knowledge of low-power design or DFT design techniques is a plus;

• Familiar with DDR, PCIE, USB, MIPI, etc high-speed interface techniques is a plus;

• Knowledge of FPGA timing constraints and timing closure background is a plus;

• Familiar with Linux OS, programming skills in Shell/Perl/Python/TCL scripts is a plus;

• Self motivated, team work, and good communication are a must.

• Design and develop deep sub-micron foundation IP circuits including standard cells, memory and customization cells for chip PPA optimization;

• Guide layout designer, assist in layout optimization based on post-layout simulation results;

• Characterize and generate design models supporting major EDA design flows including verilog, Synopsys liberty model etc;

• Design test chip testing circuits for STD/MEM/IO libraries and assist in testing.

• Minimum MS degree in EE or related majors with minimum three years experiences;

• Knowledge and project experience on circuit design with strong background on device physics;

• Familiar and hands-on experience in script language and behavior model, ie, Tcl, Perl, Verilog, etc. Experiences on Cadence/Synopsys/Mentor's EDA tools;

• Self motivated, good communication and team work skills are a must.

• Design GPIO library and customization IO, provide instruction on layout;

• Design ESD protection circuit for Analog/RF IP;

• Provide ESD protection strategy/guideline, pad cell assignment and ESD review for whole chip;

• ESD/Latchup test and Failure Analysis.

• Over 3-years of related working experience in IO & ESD design;

• M.S. in EE or equivalent;

• Knowledge in device physics, process, and physical layout;

• Deep understanding of IO ESD/Latchup protection;

• Experience on timing model and IBIS model;

• Experience on DDR/SD/eMMC/LVDS IO is preferred;

• Self-motivated, good communication skills and team work spirit are a must.

• Develop challenging analog circuits independently, including circuit design, simulation, testing, debugging and improvement;

• Determine system requirement, define project specifications according to customer’s requirement;

• Lead the project development;

• Contribute phenomenally to problem solving in circuit design, testing and debugging;

• Supervise layout development;

• Provide technical support for Customer/FAE/Sales.

• Master degree or above in EE;

• Has work experience in analog , PLL or SerDes design;

• Experience with the architecture design and production of LVDS RX/TX ,HDMI RX/TX, or DP RX/TX;

• Experience with PLL, CDR, RX, TX or Equalizer design in deep-submicron CMOS;

• Experience with SerDes PHY circuit design;

• Experience with USB3.0, HDMI, MIPI, Display Port and PCI Express Transceiver;

• Fluent in both English and Chinese;

• Self motivated, good communication skill and team work spirit.

• Draw test plan for new product and discuss with designer about test feasibility;

• Develop test program on various ATE platform for new product. Manage debug of test program and hardware and meet product release schedule;

• Support production and optimize program for test time reduction when volume ramp up;

• Support test chip development and characterization of VeriSilicon IPs.

• Bachelor degree or above in EE with 3+ years of IC test experience is a must;

• Familiar with V93k platform, RF/High Speed project development experience are preferred;

• C/C++ programming skills;

• Familiar with pattern conversion tool TDL, etc;

• Good spoken and written English skills;

• Good communication skill and team work spirit;

• Used to work in challenging cycle times.

• Plan and schedule project timelines, track project delivery milestones, and outputs;

• Coordinate functional departments and teams, including chip design implementation, software, system hardware, etc., to ensure the smooth implementation of the project;

• Monitor project progress, practice effective risk management, and ensure project deadlines are met;

• Communicate effectively with clients, understand their needs, and ensure customer satisfaction with project execution results;

• Conduct project evaluations and results assessments during and upon project completion.

Candidates who meet one or more of the following criteria will be given priority consideration:

• Master's degree with a minimum of 3 years of work experience, or a Bachelor's degree with at least five years of relevant work experience;

• Participation in the entire chip development process, understanding the complete chip design flow (design and physical implementation, design verification, system verification etc.);

• Prior experience in project management for relevant SoC or MCU chip projects is preferred;

• Knowledge of theoretical and practical aspects of project management;

• Independent work experience, with the ability to contribute to the team by solving technical, quality, cost, and schedule challenges;

• Strong communication and organizational coordination skills, proactive, strong sense of responsibility, and the ability to work well under pressure.

Design top-of-the-line Graphics/Vision processors, including specification, architecture, micro-architecture, implementation (using Verilog), and verification.

• Work experience and rank are not limited;

• Programming skills in Verilog HDL;

• Must be familiar with all stages of the ASIC design flow (including specification, architecture, and design implementation);

• Highly motivated and skillful at solving difficult technical problems;

• Knowledge of computer graphics and low-power design techniques is a plus;

• Experience of GPU design is a plus;

• Experience of memory controller design or compression design is a plus.

• Implement C-Model for HW accelerated algorithm and functionality of AI;

• Develop tests, test plans, and testing infrastructure for to verify new algorithm and functionality and their performance;

• Co-work with RTL team, cross-validate model and RTL.

• Master or PHD degree in Graphics, CS, EE, or Math, at least 3~5 years experience;

• Strong C/C++ programming skill. Familiar with Windows Visual Studio programming, and Linux programming environment,System C programming skill is a plus;

• Experience with Image Processing/memory/math hardware modeling, algorithm, or C-Model/Hardware verification is a plus;

• Perl/Python programming skill is a plus;

• Strong background in computer architecture is a good plus;

• Any experience on DL frameworks, such as TensorFlow/Caffee, is good plus;

• Good written and spoken English;

• Self motivated, team work, and good communication are a must.

• Basic ISP pipeline, advanced image analysis algorithm and related image processing algorithm research and optimization;

• ISP Algorithm C-Model design and implementation.

• MS., PHD. in EE, CS or related IT technology fields;

• Work experience and rank are not limited;

• Skilled in algorithms of ISP modules and C/C++ programming, especially 3+ years experience in design of image processing algorithm;

• Knowledgeable in ISP architecture, ASIC algorithm design and optimization;

• Good Mandarin and English communication skills;

• Self-motivated, good communication skills and team work spirit.

• Provide front-line support for the professional SoC design service and Star IPs including both digital and mixed-signal IPs;

• Tasked with providing technical consultation, training and developing example systems and application notes for customers and licensees who are developing system-on-a-chip designs for communications and consumer systems and high performance embedded software.

• Masters Degree in Electronics Engineering or Communications Engineering (Bachelors Degree considered if supported by 7+ years experience);

• 5+ years post-graduate experience of communications or consumer chip system development based on MCU/DSP;

• Knowledge on RTL and ASIC/SoC design;

• Experience of embedded software development not essential but a definite advantage;

• Good verbal and written communication in English and Mandarin essential;

• Experience in a customer-facing role preferred.

• Build and develop relationships with customers, manage customer expectations to optimize customer satisfaction;

• Follow up customers' questions on SerDes IP;

• Track and update JIRA support tracking management system to meet SLA;

• Verilog model integration and simulation;

• GDS physical integration and floorplan design;

• DFT integration;

• Timing closure;

• SerDes EVB testing;

• Firmware integration;

• Post-Silicon bring up;

• Post-Silicon validation;

• Analyze and identify characteristics of requirements.

• Bachelor degree or above majored in Electrical Engineering/Computer Science/ Communication Engineering and related;

• At least 5 years experience from SerDes product FAE or PM of semiconductor company; chip design experience is preferred;

• Familiar with SerDes or IC design/verification/manufacturing flow, familiar with software and hardware of SerDes or chip application;

• Deeply understanding on high-speed IO of advanced process (16nm/7nm/5nm)、 high-speed SerDes(28G/56G/112G)、PCI Express, or deeply understanding on advanced process IP/chip design and advanced package technology;

• Deep understanding or relevant experience on SerDes application and its technology supply chain、IP partners and customers are preferred;

• Excellent communication, organization and coordination ability, good project management ability and self-driving ability.

• Co-work with product engineer to review wafer tape out, pilot run, qualification, drive the continuous improvement;

• Plan the reliability qualification plan and execute;

• Organize the review for production release, maintain QPL list and product data base;

• Support the vendor audit;

• Handling the RMA and FA;

• Structured and effective Problem Solving Methodology, including 8D/3x5WHY, drive the vendor to continue improve quality performance.

• Bachelor degree or above in electronic and material science, major in semiconductor, EMS related;

• 3-5 years quality management experience in IC design and manufacturing house, familiar with wafer fabrication, IC assembly and Testing process;

• Familiar with quality management system including ISO9001/IATF16949, rich audit experience, can lead the audit along;

• Good quality improvement principles and tools such as 8D,3x5why etc;

• Good skill in reliability qualification, familiar with Jedec and AEC Q-100;

• Team working, fluent English, good communication skills and strong organizing capability.

• Research new technologies and innovations to develop new products and improve existing products;

• Define new feature or product specification based on in-depth understanding of customer requirements;

• Create and Control the project production plan, including cost, schedule and quality, coordinate the resource to do the trial run for NPI project in production before it transfers to mass production, mass production management, such as yield improvement, failure analysis and cost reduction;

• Work closely with Foundry and Package/testing house in both process improvement and project management; maintain good customer relationship, support and resolve their issues, identify needs and new opportunities, perform technical training, presentation, and demo to customers, sales, and engineers;

• Need to create the production concept and planning for the manufacture strategy, and evaluate the budget for product price.

• Master’s degree or above in electrical or industry engineering or related major; Good communication skills in English;

• Above 2 years working experience as product engineer or application engineering in the relevant semiconductor area;

• Have experience in one of the fields in Design house PE, Foundry PIE/PDE (Product Engineer), Package house NPI/ R&D, Testing house PTE; be familiar with FINFET Process Technology is highly preferred;

• Skillful in analysis, generate ideas, and provide innovative solutions to solve technical problems;

• Good communication skills in English.

• Monitor foundry/FA purchasing matters to meet requirement;

• Maintain daily work with vendors;

• Responsible for pricing, contracts, and payment terms with vendors;

• Work with internal team to ensure pre-sales activity;

• Daily SAP maintain.

• Possess a Bachelor or above Degree in Supply Chain Management or related fields;

• 1-2 years experience in operation team in IC related company. Good fresh student is also welcomed;

• Have a good understanding of supply chain and IC manufacturing processes;

• Have a team and project management experience is preferred;

• Good in communication and good English writing & speaking;

• Proactive and willing to learn new things and to take more task.

• Provide day-to-day technical support for desktop, laptop, Mac, IP Phone, mobile devices, network devices, telephone, printers, projectors, etc;

• Deploy, support operating systems and client software, including Windows, OS, Linux, Microsoft Office, Autodesk, Adobe Photoshop, Visual Studio, Development software, etc;

• Provide basic support for VMWare, ESXi, Windows server, storage, and network device etc;

• IT asset Management;

• Familiar ITIL support model, check cases in Helpdesk queue, and resolve in SLA;

• PC hardware troubleshooting, replace basic component;

• Vendor management, IT device order and payment management etc;

• Collect and draft IT relevant guide and document.

• Education to degree Level preferably in Computer Science relevance;

• Good English skill is preferred;

• At Least 2 years’ experience of Helpdesk support;

• Have passion and responsibility on work;

• Familiar with AD, Windows, MS Office (outlook, Excel, Word, PowerPoint);

• Basic knowledge for network device;

• Excellent learning capabilities and team work spirit;

• CCNA/MCSE/RHCE is preferred.

• Windows and Linux Level 1 support;

• Responsible for monitoring server health status.

• Bachelor of Computer science or related subjects, over 1 years of System Administrator experience;

• Good experience with Unix/Linux systems (Red, Hat, CentOS, Ubuntu), with troubleshooting capability;

• Good experience with network;

• Good communication skills and team work;

• Good English reading and writing;

• RHCE preferred.

• Wan/Lan/Wireless deployment, maintain and troubleshooting. Familiar with Cisco, Huawei’s router, Switch, Firewall etc devices;

• Manage global office’s network maintain, monitor and troubleshooting, optimize network infrastructure;

• Provide project demand network resolution;

• Manage Information security, Risk estimation, optimization and incident respond etc;

• Manage and assist to fit ISO 9001 27001 audit.

• Education to degree Level preferably in Computer Science ,information security relevance;

• At Least 3 years’ experience of relative experience;

• CCNP/HCIP CCIE/HCIE certiication is preferred;

• Familiar with TCP/IP OSPF,SPANTREE, M-Lag etc protocol;

• Familiar with security device include Firewall, anti-attack, Load balance,WAF, DDOS etc;

• Familiar with Security monitor, including port, vulnerability scanning, Penetration testing and analyze.