COMPANY

About VeriSilicon
Executive Team
Press Release
In the News
Events
Partners
Careers
Trademark
Contact Us

INVESTOR RELATIONS

Board of Directors
Major Investors
Stock Information
IR Contacts
High-Performance and Low-Power Design for Automotive

VeriSilicon Vivante DC8200-FS Display Processing IP is designed specifically for the safe display and multi-layer processing of automotive and industrial applications to minimize the risk of accidents and injuries caused by hardware-related issues. In compliance with ISO 26262 for ASIL-B, the IP provides safe mechanisms such as memory protection and register configuration path protection.

FeatureDC8200-FS-2KDC8200-FS-4K
Maximum display resolution for single output device2K@240Hz4K@60Hz
Maximum display resolution for multiple output devices2K@240Hz4K@120Hz
Display output channels supported22
Number of video/graphic and overlay layers88
10-bit format supportYesYes
Pixel rate (pixels per cycle)11
Highlights
Support for both single-OS mode and dual-OS mode
On-the-fly pixel processing pipelines
Dynamic layer allocation between the two output panels
Unified frame buffer compression
Safety Mechanism Features
Memory and registers parity
AXI, AHB parity and transaction protection
Critical unit duplication
CRC data protection
Memory ECC data protection
Safety error management unit
Layers and Pre-Processing Features
Rotation and flip
Color keying
Scaling
Programmable color space conversion: YUV-to-RGB, RGB-to-RGB
De-gamma
ROI partial image
Swizzle
QoS management
Post-Processing Features
Alpha blending
Programmable color correction matrix (CCM)
3D LUT
Gamma correction and dithering
RGB-to-YUV conversion
Display Interfaces
DP
DPI
Input Formats
A/XRGB8888, A2R10G10B10, A/XRGB1555, RGB565, A/XRGB4444, RGB888
YV12, NV12, P010 (10-bit), NV16, YUY2, UYVY, YUV444
Output Formats
RGB formats supported by DP/DPI interface: 16-bit color coding for RGB565, 18-bit color coding for RGB666, 24-bit color coding RGB888, 30-bit color coding for RGB101010
YUV formats supported by DP interface: 8/10-bit YUV444/YUV422/YUV420
Advanced and Miscellaneous Features
DDR write-back
DEC400 lossless decompression
Double-buffered register
Clock gating for RAM and each layer
MMU support
CRC-32 calculation with at most 17 regions
Software and OS Support
OS supported: Linux, Android, Windows
Drivers supported
  • Vivante DRM display driver
  • Vivante DPU display driver

Search

Contact

Language

简体中文

English

日本語

芯原股份 (688521.SH)
Thank You for Subscribing
Thank you for subscripting to receive the latest news of VeriSilicon via email .
While you await our next issue, we invite you to learn more about VeriSilicon through the resources below.
CUSTOM SILICON SERVICE
Embedded Vivante GPU, Vision, and IoT cores
Embedded Vivante Dedicated Vision IP
ZSP Digital Signal Processors
Hantro Video Encoder and Decoder IP
Company Information
Close