The embedded USB 2.0 (eUSB2) PHY is a high-speed System-on-Chip (SoC) integrated transceiver IP in advanced process that implements the Intel® UTMI standard. It provides a High/Full/Low-Speed USB analog front-end with a built-in 8-bit/16-bit parallel interface. Optimized for portable applications, the PHY features low power dissipation in active and/or standby state, and a small area for low cost. The eUSB2 PHY supports both native mode and repeater mode. In native mode, the eUSB2 PHY supports board-level chip-to-chip communication. In repeater mode, the eUSB2 PHY supports standard USB 2.0 communication with discrete USB 2.0 PHY through a separate eUSB 2 repeater component.
|
|
|
