The V-by-One receiver PHYs vx1rx4top and vx1rx8top are initially designed for Sigma Designs' frame rate converter, FRCX. In combination with a compatible V-by-One receiver MAC, they support video data reception compliant with the V-by-One HS standard.
The vx1rx4top and vx1rx8top convert the serial data streams into 10-bit wide parallel data streams and recover the clock from the data edges using an internal clock-data recovery (CDR) PLL circuit. The differential inputs are internally terminated with 100-Ω resistors, which are automatically adapted to process technology. The maximum serial data rate per lane is 4Gb/s.
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