USB 2.0 PHY

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USB2.0 PHY

The USB 2.0 PHY is a high-speed USB peripheral transceiver IP that implements the Intel® UTMI standard. It provides a High/Full/Low-Speed USB analog front-end with a built-in 8-bit/16-bit parallel interface. Optimized for portable applications, the PHY features low power dissipation in active and/or standby state, and a small area for low cost. The USB 2.0 PHY can be implemented as a discrete or integrated physical layer interface for any OTG device that complies with the On-The-Go and Embedded Host Supplement to the USB 2.0 Specification, or any host or peripheral that complies with the USB 2.0 Specification. It also supports battery charging function.

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Features

Compliant with the USB Specification Compliant with the UTMI Specification Revision 1.05 Compliant with the UTMI+ Specification Revision 1.0 Level 3 Compliant with the On-The-Go (OTG) Specification Revision 2.0 Compliant with the Battery Charging Specification Revision 1.1 Supports 480 Mbit/s “High Speed”, 12 Mbit/s “Full Speed”, and 1.5 Mbit/s “Low Speed”” Supports 60 MHz/8-bit interface and 30 MHz/16-bit interface		Supports either crystal reference clock source or on-chip reference clock source Supports multiple reference clock frequencies: 12 MHz, 19.2 MHz, 20 MHz, 24 MHz, 40 MHz, etc. Integrates 45 Ω ± 10% termination, 1.5 kΩ pull-up and 15 kΩ pull-down resistor Clock and data recovery from serial stream on the USB bus Supports detection of USB reset, suspension, resume, and remote-wake-up features Supports the test modes defined in the USB 2.0 Specification Provides Built-in-Self-Test (BIST) mode

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