The UCIe PHY IP is a market-leading, ultra low-power, and low-latency interface IP for high-bandwidth connections between two dies that are on the same substrate. The PHY IP implements a wide-parallel and forwarded-clock PHY interface for multi-channel interconnections at data rate up to 24 Gbps per pin.
The PHY IP is configurable to support the leading standards in the industry Universal Chiplet Interconnect Express (UCIe)--providing customers a Die-to-Die (D2D) solution that is compliant with industry standards.
|
|
|
