PCIe 3.0 PHY is compatible with the PCIe 3.0 (8 Gbps) standard and backward compatible with PCIe 2.1 (5 Gbps) and PCIe 1.1 (2.5 Gbps) protocols. The PHY has 1-lane, 2-lane, and 4-lane versions for flexible applications. The PHY includes a hard macro (PMA SerDes) and a soft RTL (PCS). The PHY supports common reference clocks and independent clock source configurations. The PHY also includes the Programmable Continuous Time Linear Equalizer for supporting complex PCB signal integrity cases. Multiple debugging methods such as embedded eye monitor, BIST test, and boundry scan help bug locating.
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