PCIe 2.0 PHY is compatible with the PCIe 2.0 (5 Gbps) standard. The PHY has 1-lane, 2-lane, and 4-lane versions for flexible applications. The PHY includes a hard macro (PMA SerDes) and a soft RTL (PCS). The PHY supports common reference clocks and independent clock source configurations. The PHY integrates a programmable 3-tap TX FFE, along with RX CTLE and VGAs, to ensure robust signal integrity across challenging PCB channel environments. Multiple debugging methods such as embedded eye monitor, BIST test, and boundary scan help bug locating.
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