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LVDS TX PHY

The LVDS transmitter is designed to support single link transmission between host and flat panel display with up to SXGA+ resolution. It also supports dual link transmission between host and flat panel display with up to UXGA resolution.

The IP converts 35-bit of CMOS/TTL data into LVDS data stream. The transmitter can be programmed for rising edge or falling edge clocks via a dedicated pin.

LVDS_TX_PHY.png

Features

  • Supports 25 MHz to 150 MHz clock

  • 35:5 data channel compression ratio at up to 1050 Mbps per channel data rate

  • Converts 35-bits data to 5-pair LVDS data streams

  • No external component required for PLL

  • Selectable clock edge

  • Compatible with TIA/EIA-644-A LVDS standard

  • Power down mode

  • |VOD| is changeable from 50 mV to 400 mV

  • Full industrial operating junction temperature range: -40°C to +125°C

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芯原股份 (688521.SH)
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