The LVDS Receiver IP is designed to support single link transmission between ost hand flat panel display with up to SXGA+ resolution. The LVDS Receiver IP converts the LVDS data stream back into 35 bits of CMOS data with a variety of LCD panel controllers.
The receiver LVDS clock operates at a rate between 25 MHz and 150 MHz. At an input clock rate of 150 MHz, each LVDS input line operates at a bit rate of 1.05 Gbps.

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