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Physical Layer of LVDS Receiver

The LVDS Receiver IP is designed to support single link transmission between ost hand flat panel display with up to SXGA+ resolution. The LVDS Receiver IP converts the LVDS data stream back into 35 bits of CMOS data with a variety of LCD panel controllers.

The receiver LVDS clock operates at a rate between 25 MHz and 150 MHz. At an input clock rate of 150 MHz, each LVDS input line operates at a bit rate of 1.05 Gbps.

LVDS RX PHY.png

Features

  • Functions compatible with the National DS90CF386

  • Converts a 5-pair LVDS data stream into 35 bits of parallel CMOS data

  • Wide dot clock range: 25 MHz to 150 MHz, suited for VGA, SVGA, XGA, SXGA, SXGA+, and UXGA

  • Supports up to 1.05 Gbps data rate for UXGA

  • On-chip DLL with no external component

  • Low-power CMOS design

  • Power-down control function

  • Compatible with TIA/EIA-644 LVDS standards

  • Full industrial operating junction temperature rangeL -40°C ~ +125 °C

  • On-chip 100Ω termination resistor that can be disabled

  • Negative clock edge for data output

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