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Home IP Portfolio Interface IP HDMI2.0 RX PHY
HDMI2.0 RX PHY

HDMI RX PHY is the physical layer of a single-port HDMI transmitter interface. The HDMI RX PHY comprises three data lanes and one clock lane to perform the serialization and transmission of video/audio data and control information. The PHY can support a maximum data rate of 6 Gbps/lane to satisfy HDMI 2.0 protocol. The PHY supports input data transfers of 30, 60, or 120 bits. 

HDMI2.0 RX PHY.png

Features

  • Compatible with HDMI 2.0/1.4 RX PHY operation

  • Supports deep Color modes: 24, 30, and 36 bits

  • Includes an audio clock regeneration block

  • Production test and debug capabilities

  • Supports TMDS clock range from 25 MHz to 340 MHz

  • Supports TMDS character rate from 250 MHz to 600 MHz

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