This is a D-PHY Master IP compliant with the “MIPI Alliance Spec for D-PHY v1.2”. The IP consists of 1 clock and 4 data lanes. Each data lane supports HS and LP Escape modes (LPDT, Trigger, ULPS) in the forward direction. The supported data rate per lane is 2.5 Gbps in High-Speed mode and 10 Mbps in Low-Power escape mode. Only data lane 0 is bi-directional and additionally supports Turnaround and LP Escape modes (LPDT and Trigger) in the reverse direction. Target applications are CSI-2 devices and DSI host physical layers.