This is a D-PHY RX IP compliant with the “MIPI Alliance Spec for D-PHY v1.2”. The IP consists of 1 clock and 4 data lanes. Data lane 0 supports HS and ULPS modes in the forward direction, and also supports LP Escape modes (LPDT, Trigger) and Turnaround in both forward and reverse directions. Other Data lanes support HS and LP Escape modes (LPDT, Trigger, ULPS) in the forward direction. Each lane supports a maximum of 2.5 Gbps in High-Speed mode and 10 Mbps in Low-Power escape mode. Target applications are CSI-2 host and DSI device physical layers.
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