The VS_MIPI_CSI2_HOST is a CSI-2 Host Controller that provides a standard, robust, scalable, high-speed, cost-effective interface that supports a wide range of image data transmission solutions for image sensors. The VS_MIPI_CSI2_HOST IP resides in the SoC or bridge chip, The function of this IP is to receive and processe image data or forward these data to A-PHY SRC or ISP system.
This CSI-2 interface IP is fully compliant with MIPI Alliance Standard Specification for Camera Serial Interface 2 (CSI-2), Version 3.0. It supports up to 4 MIPI D-PHY RX data lanes and up to 3 MIPI C-PHY RX data trios (hardware configurable). It supports primary and secondary image formats including YUV, RGB, RAW, and user-defined data formats. It also supports configurable pixel throughput of 1, 2, 4, 6, 8 pixels per pixel clock. Additionally, error detection and interrupt for PHY Protocol Interface (PPI) data receiving, protocol parsing, and interface converting are available.
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