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Home IP Portfolio Interface IP MIPI C/D-PHY TX
MIPI C/D-PHY TX

This IP is a C/D Combo PHY TX IP which can be flexibly configured as Master D-PHY or C-PHY. It can support camera interface CSI-2 v1.3 and display interface DSI-2 v1.0 applications in both D-PHY and C-PHY modes. It can also support DSI v1.3 applications in D-PHY mode. It can work with both old D-PHY and new C-PHY systems.

The C-PHY is based on 3-Phase symbol encoding technology delivering 2.28 bits per symbol over three-wire trios, and operates with a symbol rate range of 80 to 4500 Msps per trio, which is the equivalent of about 182.8 to 10285 Mbps per trio.

Each lane of the D-PHY supports 80 to 4500 Mbps in High-Speed mode and 10 Mbps in Low-Power escape mode.

CD-PHY TX.png

Features

  • Complies with the MIPI D-PHY spec v3.0

  • Complies with the MIPI C-PHY spec v2.1

  • Supports HiSPi-SLVS TX compatible mode

  • 80 to 4500 Mbps data rate per lane in D-PHY HS mode (The maximum throughput is 18 Gbps with 4 data lanes

  • 80 to 4500 Msps symbol rate per trio in C-PHY HS mode (The maximum throughput is 30.78 Gbps with 3 trios)

  • 10 Mbps data rate in Low-Power Mode

  • Supports 3 data lanes for C-PHY Mode

  • Supports 1 clock and 4 data lanes for D-PHY Mode

  • All lanes support HS and ULPS modes in forward direction

  • All data lanes support Escape mode (LPDT, Trigger) in forward direction

  • D0/T0 lane supports reverse Escape mode (LPDT, Trigger) and Turn-Around in LP mode

  • Supports HS-TX half swing for D-PHY

  • Supports HS De-skew, Alternate calibration sequence and Preamble sequence

  • Supports LVLP mode

  • On-chip calibration for driver impedance

  • Ultra low current in Shutdown and ULPS mode

  • Built-in self-test function

  • ASIL-B Functional Safety certified

  • AEC-Q100 Grade 1 qualified

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