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Home IP Portfolio Interface IP MIPI C/D-PHY RX
MIPI C/D-PHY RX

This IP is a C-PHY/D-PHY Combo RX IP which can be flexibly configured as Slave D-PHY or C-PHY. It can support camera interface CSI-2 and display interface DSI-2 applications in both D-PHY and C-PHY modes. It can work with both old D-PHY and new C-PHY systems.

The C-PHY is based on 3-Phase symbol encoding technology delivering 2.28 bits per symbol over three-wire trios, and operates with a symbol rate range of 80 to 4500 Msps per trio, which is the equivalent of about 182.8 to 10285 Mbps per trio.


Each lane of the D-PHY supports 80 to 4500 Mbps in High-Speed mode and 10 Mbps in Low-Power escape mode.

MIPI CD-PHY RX.png

Features

  • Complies with the MIPI D-PHY spec v3.0

  • Complies with the MIPI C-PHY spec v2.1

  • 80 to 4500 Mbps data rate per lane in D-PHY HS mode (The maximum throughput is 18 Gbps with 4 data-lanes)

  • 80 to 4500 Msps symbol rate per trio in C-PHY HS mode (The maximum throughput is 30.78 Gbps with 3 trios)

  • Three 3-phase encoded data lanes for C-PHY Mode (T0 lane is bi-dir)

  • Supports one clock and four data lanes for D-PHY Mode (D0 lane is bi-dir)

  • All lanes support HS and ULPS modes in forward direction

  • All lanes support Escape (LPDT, Trigger) mode in forward direction

  • D0 lane supports reverse Escape mode (LPDT, Trigger) and Turn-Around in LP mode

  • Supports HS half swing for D-PHY

  • Supports HS De-skew, Alternate calibration sequence and Preamble sequence

  • Supports LVLP mode

  • Supports terminated and un-terminated modes

  • Ultra low current in Shutdown and ULPS modes

  • On-chip calibration for termination impedance

  • Built-in self-test function

  • ASIL-B Functional Safety certified

  • AEC-Q100 Grade1 qualified

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