The 12.5 Gbps to 16 Gbps high-speed SerDes (HSS) is compatible with multiple industry protocols. The PHY has 1-lane, 2-lane, and 4-lane versions for flexible applications. Additionally, HSS supports wide range datarates and multiple parallel data width. HSS also includes 3-tap programmable TX FFE, CTLE, and VGAs to maintain signal integrity across complex PCB environments. Multiple debug methods such as embedded eye monitor, BIST test, and boundary scan are provided to facilitate bug locating.

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