Vivante DC8000

首页 IP 组合 Vivante^® 显示处理器IP Vivante DC8000

Scalable and flexible display processor

VeriSilicon's Vivante DC8000 Display Processor family is designed specifically for Wearable, MCU, MPU, and Mobile applications that need hardware UI displays and effects. It is absolutely essential for building efficient mobile and embedded systems targeting the next generation of displays to meet rising consumer expectations for appealing UI. Vivante DC8000 Display Processor IP provides a range of low-power and high-performance display cores that can be used for reading rendered images from the frame buffer. In addition to providing hardware cursor patterns, the display processor performs format conversions, dithering, and gamma corrections.

Addressable screen sizes range from the smallest wearable devices, IoT devices, cell phones to 4K resolutions. Vivante DC8000 Display Processor IP is designed for easy integration onto the SoC, providing powerful UI, graphics, video at the lower power consumption and the smaller of silicon footprints.

Leading Performance per Area

"Push button" reference flow for Cadence and Synopsys

100 ps clock uncertainty

Test insertion ready

Extreme Low Power Design

Intelligent power management and control

Automatic hardware dynamic power control

Software controlled power states

Automatic clock/power gating of flip flops, RAMs, and functional blocks

Display Output

Parallel pixel output with 24-bit or 30-bit data

DPI 24-bit, 18-bit (2 configs) and 16-bit support (3 configs)

Adaptable to external serialization logic, e.g. HDMI

AXI bus Interfaces

64-bit or 128-bit AXI

Optional ACE-Lite

Bursts to 128 bytes (64-bit AXI) /256 bytes (128-bit AXI)

Display Control

Dual Display available with: Independent clock bits and gating controls; Dither LUT for each display; Independent sync and gamma signals; Cursor can be shared across displays

Scaling and Rotation of input surfaces available

Input formats supported: ARGB8888, ARGB1555, RGB565, ARGB4444, YUV422-YUY2 YUV422-UYVY, YUV422-NV16, YUV420-NV12, YUV420-10bit semi-planar

Unified Compression Support

Hardware Deliverables

Synthesizable Verilog RTL

Memory specifications

SoC integration test suites

System diagnostic tests (FPGA and SoCsystems)

FPGA bit file (Xilinx) for prototyping

Timing constraints

Reference floor plan definition

Reference implementation flow

Reference formal verification script

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