The VX1 Transmitter AFE receives 10-bit parallel data per lane from the digital core. This data is latched inside the VX1 AFE and then serialized by the serializer with the least significant bit (LSB) transmitted first. After serialization, the serial bit stream is sent to the pre-driver and driver. The driver converts incoming digital signals to analog signals and transfers them to the receiver chip. The VX1 Transmitter uses a half-rate clock system and multiplexes even and odd data using the adjustable PLL output clock.
|
|
