The SD/eMMC PHY provides the physical interface between the digital controller and external memory storage, such as SD cards or eMMC chips. The PHY includes delayline, DigiLogic, and high speed IO which are compliant with SD/eMMC protocol. The SD/eMMC PHY I/O signal voltage is within 3.3V/1.8V. This IP supports SD3.1 and eMMC5.1, including dual data rate for DDR50 and HS400, and single data rate for SDR104 and HS200.
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