This is a DPHY Master IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of 1-Clock and 4-Data lanes. Each data lane can support HS and LP Escape modes (LPDT, Trigger, ULPS) in forward direction. The supported data rate per lane is 2.5Gbps in High-Speed mode and 10Mbps in Low-Power escape mode. Only data lane0 is bi-directional and can additionally support Turnaround and LP Escape mode (LPDT and Trigger) in reverse direction. The target applications are CSI-2 device and DSI host physical layers.
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