This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of 1-Clock and 4-Data lanes. Data lane0 supports HS support and ULPS in the forward direction, and supports LP Escape modes (LPDT, Trigger, ULPS) and Turnaround in both forward and reverse direction; Other Data lanes support HS and LP Escape modes(LPDT, Trigger, ULPS) in the forward direction. Each lane supports 2.5Gbps in High-Speed mode and 10Mbps/lane in Low-Power escape mode. The target applications are CSI-2 host and DSI device physical layers.
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