公司

关于芯原
管理团队
新闻发布
公司动态
市场活动
合作伙伴
加入我们
商标
联系我们

投资者关系

董事成员
主要投资者
股票信息
投资者联系
可持续发展报告
首页 IP 组合 接口IP MIPI DSI Device Controller
MIPI DSI Device Controller

The VS_DSI2_Device_Controller is a MIPI-compliant digital controller that resides on the display side of the link, serving as the bridge between the host system and the physical layer. It receives DSI-2 commands and data from the Host Controller Core through 1 to 4 D-PHY or C-PHY lanes, then reassembles the protocol packets for the display pipeline.

This DSI-2 interface IP core is fully compliant with MIPI Alliance Standard for Display Serial Interface 2 (DSI-2) Version 2.2. It supports both D-PHY (up to 4 lanes) and C-PHY (up to 3 trios) interfaces with configurable PPI widths for high-speed and low-power operation. The IP provides an enhanced DPI supporting both video and command modes with programmable signal polarity. It also supports a wide range of video mode formats per DSI-2 v2.2, including various YCbCr, RGB, and compressed pixel streams up to 48-bit. In addition to BIST (color bar) mode, comprehensive error detection is implemented, covering PHY, packet, protocol, and FIFO status. 

DSI Device Controller.png

Features

  • Compliant with MIPI Alliance and AMBA standards

    -  MIPI Alliance Standard for Display Serial Interface (DSI-2) Version 2.2 compliant

    -  MIPI Alliance Specification for C-PHY Version 2.1 compliant

    -  MIPI Alliance Specification for D-PHY Version 3.0 compliant

    -  AMBA 3.0 Specification (APB) from Arm

  • Supports MIPI C-PHY 16-bit, D-PHY 8/16-bit data width PHY Protocol Interface (PPI) as output

  • Multiple sync modes

    -  Non-burst mode with sync pulses

    -  Non-burst mode with sync events

    -  Burst Mode

  • Supports D-PHY high-speed and low-power operation, C-PHY high-speed and low-power operation

  • Supports programmable scrambling

  • Supports blanking and NULL packet

  • Supports normal or inverted HSYNC and VSYNC signals

  • Supports the full range of DSI-2 pixel streams, including Compressed Pixel Stream (Data Type 0x0B, up to 48-bit)

    -  Loosely Packed Pixel Stream, 20-bit YCbCr, 4:2:2 format (Data Type 0x0C)

    -  Packed Pixel Stream, 24-bit YCbCr, 4:2:2 format (Data Type 0x1C)

    -  Packed Pixel Stream, 16-bit YCbCr, 4:2:2 format (Data Type 0x2C)

    -  Packed Pixel Stream, 30-bit RGB, 10-10-10 format (Data Type 0x0D)

    -  Packed Pixel Stream, 36-bit RGB, 12-12-12 format (Data Type 0x1D)

    -  Packed Pixel Stream, 12-bit YCbCr, 4:2:0 format (Data Type 0x3D)

    -  Packed Pixel Stream, 16-bit RGB, 5-6-5 format (Data Type 0x0E)

    -  Packed Pixel Stream, 18-bit RGB, 6-6-6 format (Data Type 0x1E)

    -  Loosely Packed Pixel Stream, 18-bit RGB, 6-6-6 format (Data Type 0x2E)

    -  Packed Pixel Stream, 24-bit RGB, 8-8-8 format (Data Type 0x3E)

  • Supports configurable 2 ppc or 1 ppc in DPI interface in video mode

  • Configurable SRAM size

  • Supports Colorbar mode in video mode

搜索

联系

语言

简体中文

English

日本語

芯原股份 (688521.SH)
感谢您的订阅
感谢您通过邮件.订阅芯原的最新消息。在您等待我们网站的下次更新时,我们邀请您通过以下资源来了解芯原的更多信息。
芯片定制解决方案
Vivante图形处理器IP
Vivante神经网络处理器IP
ZSP数字信号处理器IP
Hantro视频处理器IP
关于芯原
关闭