PCIE PHY

首页 IP 组合数模混合IP PCIE PHY

This 1-lane to 4-lane PCIE PHY includes all high-speed analog functions for high-speed data transport between chips over PCBs and high quality cables. It can support different data rates (2.5Gbps to 8Gbps) for compatible with PCIe1.1, PCIe2.1 and PCIe3.1 protocols. It is optimized for low power operation and is suitable for 8b, 10b, 16b, 20b input data path width.

For long trace signal transmission, the PCIe PHY contains programmable 3-tap FFE, CTLE and 5-tap DFE with adaptive algorithm. In-built Eye Monitor can help analysis internal high-speed signal and BIST function is useful for production test.

Features

Programmable 5 tap Decision Feedback Equalizer (DFE) to improve received signal integrity Comprehensive power-down control to optimize power modes Built-in Self-Test (BIST) features for production Compatible with PCIe1.1, PCIe2.1 and PCIe3.1 Programmable TX Feed Forward Equalizer Design in GLOBALFOUNDRIES 22nm FDX Core area: 2042280um^2		Programmable serialization, de-serialization data width: 8, 10, 16, 20 bit Adaptive algorithm for RX Analog Front End (AFE) and DFE Receiver detection and LOS detector circuitry In-built Eye Monitor for link analysis Power consumption: - 300mW@PCIe1.1 - 380mW@PCIe2.1 - 450mW@PCIe3.1

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