LVDS TX PHY

首页 IP 组合数模混合IP LVDS TX PHY

The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolution and Dual Link transmission between Host and Flat Panel Display with up to UXGA resolution.

The IP converts 35-bit of CMOS/TTL data into LVDS data stream. The transmitter can be programmed for rising edge or falling edge clocks via a dedicated pin.

Features

Silicon Proven in 22,28,55,65,130n,180n from SMIC, Global Foundries and Samsung Compatible with the National DS90CF386 Compatible with the TIA/EIA-644 standards Converts 35 bits data to 5-pair LVDS data stream Supports up to 1.05Gbps data rate for UXGA Clock edge selectable		Wide dot clock range: 25 ~ 150MHz suited for VGA, SVGA, XGA, SXGA, SXGA+ and UXGA Output range is changeable from 50mV to 400mV Core area: 0.5430mm^2 Power consumption: - 175.4mW@1.05Gbps, prbs7 pattern

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