ZSP® DSP Cores
Ultimate Design for SoC integration and targeted applications |
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VeriSilicon offers the industry's only software-compatible family of DSP cores to scale from ultra low cost (ZSP® neo) to ultra high performance (ZSP® 800). No other licensable DSP vendors can span such broad spectrum of performance, power and cost while maintaining compatibility. Customers choosing the ZSP architecture can be safe that their current needs are serviced and reuse their R&D investment for a wide range of new products.
As the mark of a true open architecture, all ZSP cores are available as licensable and synthesizable soft cores.
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Core |
ZSP®neo |
ZSP®200 |
ZSP®210 |
ZSP®400 |
ZSP®410 |
ZSP®500 |
ZSP®520 |
ZSP®540 |
ZSP®560 |
ZSP®600 |
ZSP®800 |
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Number
of MACs |
1 |
1 |
1 |
2 |
2 |
2 |
2 |
4 |
4 |
4 |
4 |
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Number
of ALUs |
1 |
2 |
2 |
2 |
2 |
5 |
5 |
6 |
6 |
6 |
6 |
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Instructions
/ Cycle |
1+1 |
2+1 |
2+1 |
4 |
4 |
4 |
4 |
4+1 |
4+1 |
6 |
4+1 |
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Instruction Cache |
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Data Cache |
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Z.TurboTM |
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Sample Applications |
ZSP®neo |
ZSP®200
ZSP®210 |
ZSP®400
ZSP®410 |
ZSP®500
ZSP®520 |
ZSP®540
ZSP®560 |
ZSP®600 |
ZSP®800 |
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Toys |
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Voice Synthesis |
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Embedded Control |
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Voice Over IP |
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Portable Audio |
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High Definition Audio |
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2-2.5G Wireless |
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3G Wireless |
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Mobile Video |
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WiMAX Mobile Subscriber Line |
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<, /P> |
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Software Defined Radio |
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Wireless/WiMAX Base-Stations |
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ZSPneo
The ZSPneo core is a new breed of processor highly optimized to minimize die size and power consumption and combining the capabilities of a DSP and an MCU on a single core. It is ideal for cost sensitive applications such as 1-2 channel VoIP, audio players, speakerphones, wireless application processors, toys, servo and automotive controls that require performance above existing 8-bit microcontrollers, but cannot tolerate the unnecessary cost of 32-bit microcontrollers.
ZSP200
The ZSP200 supports up to 2 instructions per cycle with parallel MAC and ALU. Designed for voice, audio, control or security applications, the ZSP200 is ideally suited for ultra low-cost designs.
ZSP210
The ZSP210 is the newest ZSP product introduction. A number of features have been added to the ZSP210 to further address the low-cost and performance requirements of a number of market segments. The ZSP210 utilizes a 0-, 1- or 2-way set associative configurable instruction cache up to 64KW. |
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ZSP400
The ZSP400 supports up to 4 instructions per cycle with parallel Dual MAC and Dual ALU and a 5-stage pipeline. Designed for medium-level performance, low-cost audio, wireless and voice-processing applications, the ZSP400 has found wide acceptance in cellular, VoIP, and consumer audio products worldwide.. |
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ZSP410
A number of features have been added to the ZSP410 to further address the low-cost and performance requirements of a number of market segments. The ZSP410 utilizes a 0-, 1- or 2-way set associative configurable instruction cache up to 64KW. |
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ZSP500
The ZSP500 supports 4 instructions per cycle with an enhanced parallel Dual MAC / ALU combo plus Dual ALU and 8-stage pipeline. It features the Z.TurboTM accelerator and instruction set enhancements of the ZSP G2 architecture. It is designed for 3G wireless baseband / multimedia and multi channel audio processing. |
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ZSP520
As DSPs are being used more and more to perform the functions typically done on a CPU, the ZSP architectures continue to improve to meet these changing requirements. The ZS, P520 adds configurable instruction, and data cache support to the ZSP500 architecture as well as 32 bit addressing to efficiently tackle large applications typically done by a general purpose processor.
ZSP540
The ZSP540 supports 4 instructions per cycle with an enhanced parallel Quad MAC / Dual ALU combo plus Dual ALU and 8-stage pipeline. It features the Z.TurboTMaccelerator and instruction set enhancements of the ZSP G2 architecture. Its unmatched high performance, power and memory efficiency make it ideal 3G / 4G / WiMAX baseband processing and High Definition multi channel audio processing. |
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ZSP560
As DSPs are being used more and more to perform the functions typically done on a CPU, the ZSP architectures continue to improve to meet these changing requirements. The ZSP560 adds configurable instruction and data cache support to the ZSP540 architecture as well as 32 bit addressing to efficiently tackle large applications typically done by a general purpose processor.
ZSP600
The ZSP600 supports 6 instructions per cycle with an enhanced parallel Quad MAC / Dual ALU combo plus Dual ALU and 8-stage pipeline. It features the Z.TurboTM accelerator and instruction set enhancements of the ZSP G2 architecture. The ZSP600 core is ideally suited for base station and network infrastructure applications.
ZSP800
The ZSP800 has been developed by studying the needs of high-performance applications such as high definition audio and wireless processing. For a 65 nm process, the eight-stage ZSP800 achieves 400 MHz under worst case operating conditions. The processor can issue up to 4 16/32-bit instructions per cycle across a mixed 16/32-bit width datapath, which incorporates 6 ALUs and a Quad-MAC. The ZSP800 orthogonal DSP ISA features a number of unique application oriented instructions to significantly speed up processing. The resulting ZSP architecture achieves dramatic MHz savings when compared to other licensable processors in the market. |
Hard Cores
The ZSP hard cores are GDSII cores optimized and available on popular foundry processes. |
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